What is the SLVS-EC RX IP Core and what is it used for?
The FRAMOS SLVS-EC RX IP Core is a software solution that enables modern, high-resolution sensors to communicate with embedded hardware. The IP core is loaded onto an FPGA, where it acts as a receiver of image sensor data. The main task of the IP core is to convert bytes into pixels. The interface is Sony’s SLVS-EC solution, which is now available in version 3.0.
Instead of spending a lot of time and money developing their own data transfer solution, customers can use the IP core to quickly start integrating the sensors and hardware, thus minimizing time to market and reducing project risks thanks to a proven and reliable solution.
FRAMOS offers its SLVS-EC RX IP core for AMD Xilinx platforms together with comprehensive support, an evaluation kit and a reference implementation for the current release in version 3.0 of the SLVS-EC sensor interface. The new SLVS-EC version 3.0 supports transfer rates of up to 10 Gbit/s and up to 8 lanes per interface, and thus twice the data rate of the previous version 2.0 of SLVS-EC. The IP core supports all functions of the SLVS-EC 3.0 standard and is backwards compatible with earlier standards. It supports common pixel formats from 8 to 16 bits; these can be dynamically changed during operation. Furthermore, the error detection and the error correction (ECC: Error Correction Code) is an integral part of the IP core. The error correction can be optionally activated to further increase the robustness of data transmission. In addition, the IP core offers flexible support for different lane configurations and data handling of overlapping ROIs (Region of Interest) according to the standard.
Engineers developing imaging solutions with AMD-Xilinx FPGAs and SoCs with integrated FPGA on the board can use the FRAMOS SLVS-EC RX IP Core to conveniently develop solutions for demanding imaging applications, such as those required in medical technology, with less risk while benefiting from the advantages of the latest Sony high-speed interface. To test the waters, one of the three available evaluation kits can be used to determine how SLVS-EC v3.0 works with FRAMOS hardware and the corresponding developer board from AMD-Xilinx, and whether the purchase is worthwhile for the customer.
FRAMOS IP Core in a comprehensive evaluation kit
The FRAMOS SLVS-EC RX IP Core Evaluation Kit for Xilinx FPGAs and SoCs offers a ready-to-use hardware environment that is fully integrated into the FRAMOS Sensor Module Ecosystem. It supports customers in the evaluation and enables the integration of the FRAMOS IP Core into typical camera designs based on an exemplary, fully documented image pipeline.
The development kit contains, among other things:
- FRAMOS Sensor Module (FSM) with C/CS-mount
- FRAMOS Sensor Adapter (FSA)
- FRAMOS Processor Adapter (FPA)
- 1/4 inch tripod adapter
- flex cable
- time-limited IP core and reference designs
All in all, the comprehensive equipment of the evaluation kit offers developers the best possible support. The reference design is an example that makes the work of developers of camera systems significantly easier and considerably reduces time to market.
“Our IP core makes the future tangible here through its ease of use, allowing vision system developers to focus on what is important: the application,” – Giuseppe Contini, Technical Imaging Expert at FRAMOS
Benefit from all the advantages of SLVS-EC 3.0
SLVS-EC 3.0 allows the performance of the latest premium sensor technology to be fully utilized, e.g. in the Pregius S series and in future high-resolution sensors designed for demanding, high-resolution imaging. SLVS-EC also enables greater design freedom, simpler PCB designs, and more robust signal paths, since there are fewer pins and conductors to consider. Controlling the inherent noise of the numerous complex components and solving the associated problems requires not only imaginative designers, but also tolerant technologies.
The advantages compared to similar interfaces, such as SLVS, Sub-LVDS, MIPI CSI-2, are clear: longer signal paths, greater tolerances in the design and manufacture of cable routes, and greater flexibility in terms of interconnection and cabling. Thanks to the embedded clock and the error detection and correction functions, SLVS-EC 3.0 meets the requirements of the most advanced embedded vision systems.
Various applications in different markets
Nathan Dinning, Head of Product Management at FRAMOS, says: “Even at the launch of SLVS-EC 2.0, we were increasingly seeing a demand in the market for higher per-lane bandwidths, specifically in high-end applications, in order to reduce design effort. At the same time, we know from our own experience how standardized and feature-rich interfaces can greatly modularize and simplify integration even at the sensor level. We see applications every day that benefit from these new sensor generations and SLVS-EC, where short design cycles are necessary.” And he adds: ”The new version 3.0 of SLVS-EC is an enabler technology. The latest sensors with the help of our IP core will further reduce the effort required to develop industrial high-speed and batch scan systems, where large amounts of data currently still have to be transmitted over dozens of LVDS data lines. Special image processing projects that require robust data transfer via cables within the device will also benefit from this technology, for example, in high-resolution image capture in quality control, in satellite-based recording systems, in area mapping, as well as in document scanning or in microscopy.”
For more information about SLVS-EC, our SLVS-EC RX IP core and the evaluation kits, please visit: FRAMOS SLVS-EC RX IP CORE
