“Stacked Pixel” Technology Brings High Performance for Miniaturized Embedded Vision
The newly developed Pregius S line is the 4th generation of Sony CMOS image sensors incorporating Pregius™ technology. The Pregius S reaches higher performance in a smaller package with stacked image sensor technology that is based on Sony’s proprietary Global Shutter function, and a back-illuminated pixel structure. This technology allows smart embedded applications in industrial vision to benefit from imaging performance that is improved by 1.7X, while the form factor of sensor design is reduced by 40 percent. First samples of Sony’s new Pregius S line will be available from global vision partner FRAMOS®.
The Pregius S technology delivers both distortion free, high imaging performance and miniaturization, for applications in manufacturing, inspection and logistics. It provides higher precision and processing speeds for further advancements in the smart factory and increased levels of automation. The principal advantage of this new stacked technology is the location of the memory area and the associated wiring. Previously, front-illuminated CMOS architecture stored charged signals next to the photodiode to avoid read-out time-shifts and related image distortion, and to protect the video signals from light leakage. Conversely, this earlier structure had limited incidental light and created saturation issues associated with miniaturization.
Sibel Yorulmaz-Cokugur, the Sensor Expert at FRAMOS, says: “The technical development and global competition always require higher performance in a smaller package; that’s the driver for future applications and innovation. Sony’s Semiconductor Solutions R&D department has achieved a perfect result with the 4th generation of CMOS Global Shutter sensors, based on their excellent technical expertise. The new Pregius S line combines improved performance together with miniaturization, and enables customers to leverage increased productivity and smart applications in Embedded Vision and Automation.”
Metal wiring in the new back-illuminated structure is placed under the photodiodes. Therefore, pixel size can be reduced from a conventional 3.45µm to 2.74µm, while maintaining sensitivity and saturation quality, and achieving 1.7 times higher resolution. Where conventional front-illuminated CMOS technology achieved a resolution of 12 Megapixels, the Pregius S line can reach a potential of 20 Megapixels*. This performance is realized with a Quantum Efficiency (Peak QE) of over 20%, +44% saturation signal volume per unit area, and +12% in dynamic range. Also, the new structure allows 1.4 times more frames, leading to 2.4X faster output data rates, and a significant boost in high-speed throughput. Industrial applications benefit from performing product inspections at wider fields of view with increased accuracy and shorter measurement periods; additionally, this feature creates a 3X improvement in productivity and efficiency.
Also, the new stacked CMOS architecture offers multiple capabilities to mount additional signal processing circuits; to enable further miniaturization; and, to enhance sensor functionalities. Data optimization functions like smart ROI, self-trigger, compression processing, and compositing, reduce the processing load and the amount of data with a smaller form factor.
The new Pregius S line will be available in the Fall of 2019. The industry and product experts at FRAMOS are available to support customers with the integration of these new sensors into their applications and projects. Also for the Pregius S sensors, FRAMOS Engineering will offer services and IP around the SLVS-EC interface, such as their SLVS-EC IP core for Xilinx FPGAs. In addition, FRAMOS provides a broad range of support services for development, customization, and logistics.
* Comparison of a 1.1-type sample using this technology with Sony’s IMX253 1.1-type 12 effective megapixels front-illuminated CMOS image sensor.