| Manufacturer | FRAMOS |
|---|---|
| Product Type | IP Core, Source Code (VHDL) |
| Target Device Type | FPGA, SoC, Supported AMD Architectures: 7-Series FPGA and SoC family, Ultrascale™ FPGA family, Ultrascale+™ FPGA and SoC family, Kria™ K26 SOM, Versal™ family |
| Specification | Supports Sony SLVS-EC up to v3.0 standard, Receiver FPGA module performing byte-to-pixel conversion from incoming SLVS-EC data stream |
The SLVS-EC RX IP Core reduces overhead and complexity by implementing a SONY imager with SLVS-EC. As an on-chip function block connecting the customer’s FPGA logic with the image sensor’s data stream, the IP Core receives the interface data, manages the byte-to-pixel conversion for various lane configurations, and thus prepares a highly efficient processing workflow run on the FPGA. The FRAMOS software supports SLVS-EC v1.2, v2.0, and v3.0 with 1, 2, 4, and 8 lanes configurable by the user and delivers pixel formats from 8 to 16-bit of raw data. By de-risking the sensor implementation it significantly reduces the development efforts and accelerates the time to market.
Supported Standard and Features:
| Feature | Description |
|---|---|
| Compatible Standards | SLVS-EC v1.2, v2.0, v3.0 |
| Lanes Supported | 1, 2, 4, 8 (configurable by user) |
| Baud Grade(s) | [1]: 1.2 Gbps, [2]: 2.5 Gbps, [3]: 5 Gbps, [4]: 10 Gbps |
| Pixel Format(s) | 8, 10, 12, 14, 16 bits per pixel (RAW) (Dynamic mode change) |
| Embedded Data | Supported |
| CRC / ECC | Supported (Configurable) |
| ROI Overlapping | Supported |
The IP Core is available for the following devices:
An appropriate Evaluation Kit is available separately. Compatibility to further devices on request.
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