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SLVS-EC v1.2 RX IP Core Xilinx Encrypted
Type:
IP Core, Encrypted RTL
Further Specification:
Receiver FPGA module performing byte-to-pixel conversion from incoming SLVS-EC data stream
Product information "SLVS-EC v1.2 RX IP Core Xilinx Encrypted"
The SLVS-EC RX IP Core reduces overhead and complexity implementing a SONY imager with SLVS-EC. As on-chip function block connecting the customer’s FPGA logic with the image sensor’s data stream, the IP Core receives the interface data, manages the byte-to-pixel conversion for various lane configurations and thus prepares a highly-efficient processing workflow run on the FPGA. The FRAMOS software supports SLVS-EC v1.2 with 1, 2, 4, 8 lanes configurable by the user and delivers pixels formats from 8 to 14-bit of raw data. By de-risking the sensor implementation it significantly reduces the development efforts and accelerates the time to market.
