| Manufacturer | FRAMOS GmbH |
|---|---|
| Product Type | IP Core, Encrypted RTL |
| Supported Devices | Xilinx Artix-7™, Kintex-7™, Zynq-7000™ SoC, Kintex UltraScale™, Kintex UltraScale+™, Zynq UltraScale+™ MPSoC, Kria™ K26 |
| Target Device Type | FPGA, SoC |
| Specification |
The SLVS-EC RX IP Core reduces overhead and complexity implementing a SONY imager with SLVS-EC. As on-chip function block connecting the customer’s FPGA logic with the image sensor’s data stream, the IP Core receives the interface data, manages the byte-to-pixel conversion for various lane configurations and thus prepares a highly-efficient processing workflow run on the FPGA. The FRAMOS software supports SLVS-EC Standard v1.2 and v2.0 with 1, 2, 4, 8 lanes configurable by the user and delivers pixels formats from 8 to 14-bit of raw data. By de-risking the sensor implementation it significantly reduces the development efforts and accelerates the time to market.
Supported Standard and Features:
| Compatible Standards | SLVS-EC v1.2, v2.0 |
| Lanes Supported | 1, 2, 4, 8 (configurable by user) |
| Baud Grade(s) | [1]: 1.2 Gbps, [2]: 2.5 Gbps, [3]: 5 Gbps |
| Pixel Format(s) | 8, 10, 12, 14, 16 bits per pixel (RAW) (Dynamic mode change) |
| Embedded Data | Supported |
| CRC / ECC | Supported (Configurable) |
| ROI Overlapping | Supported |
An appropriate Evaluation Kit is available separately. Compatibility to further devices on request.
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9:00 – 17:00 Uhr
